Since a non-volatile memory device is capable of erasing or storing data electrically and allows data to be conserved without supplying power thereto, applications of the non-volatile memory device tend to increase in various fields. Such the non-volatile memory device is representatively classified into a NAND type and a NOR type. The NAND type is mainly used for storing data, whereas the NOR type is mainly used for booting an electric device such as a computer.
Meanwhile, the NOR type non-volatile memory device connects a plurality of memory cells composed of one transistor to one bit line in parallel and formed of a structure that only one memory cell transistor is connected between a drain coupled to the bit line and a source region coupled to a common source line. The NOR type non-volatile memory device has advantages that a current is high in the memory cell has a high current and is capable of being operated at a high speed, whereas it has a shortcoming that a high integration is difficult since a contact of the bit line and the common source line occupy large spaces.
In the NOR type non-volatile memory device, since a plurality of memory cells is connected to a bit line in parallel, if a threshold voltage of a memory cell transistor becomes lower than a voltage, e.g., 0V, applied to a word line of a non-selected memory cell, there occurs an erroneous operation that all memory cells are read as an on-state by flowing the current between the source and the drain regardless of the on/off states of the selected memory cell. In order to overcome such problems, a non-volatile memory device having a structure generally referred to as a split-gate type has been introduced.
Meanwhile, a non-volatile memory device can be classified into a flash memory device having a stacked gate structure of a floating gate tunnel oxide (FLOTOX) structure and a silicon-oxide-nitride-oxide-silicon (SONOS) device has a structure similar to the MOS transistor and is provided with a multi-layered gate insulating layer. A gate insulating layer of the SONOS device generally has a structure(ONO layer: Oxide-Nitride-Oxide) obtained by sequentially stacking a silicon oxide layer, a silicon nitride layer and a silicon oxide layer as a plurality of insulating layers for storing charges; and, since the charges are stored at a deep level trap of the nitride layer, the non-volatile memory device has an excellent property in reliability in comparison with the flash memory device and allows a writing operation and an erasing operation at a low voltage.
FIG. 1a to FIG. 1c are cross-section views showing a method of manufacturing a conventional split-gate type non-volatile memory device. FIG. 1a to FIG. 1c show cross-sectional views vertical to a word line.
Referring to FIG. 1a, an active region 11 is defined by forming a device isolation layer(not shown) on a semiconductor substrate 10 in parallel to a direction of a bit line. And, a multi-layer of a charge storage layer 14, a first conductive layer 16 and a capping layer 18 and 20 are formed on the semiconductor substrate 10 with a predetermined width in parallel with the word line. Herein, an ONO layer can be utilized as the charge storage layer 14 and the capping layers 18 and 20 can be obtained by stacking the silicon oxide layer 18 functioning as a buffer and a silicon nitride layer 20 used as a hard mask. Thereafter, a sidewall insulating layer 22 is formed by performing an oxidation process to a sidewall of the first conductive layer 16 in order to cure the sidewall damaged during a process of forming the first conductive pattern 16.
Sequentially, after a portion of the multi-layer charge storage layer exposed on an active region 11 is removed except the multi-layer charge storage layer 14 below the first conductive pattern 16, a gate insulating layer 24 is formed on an active region of the exposed substrate.
In the next step, referring to FIG. 1b, a second conductive layer 26 is conformally formed on the gate insulating layer 24 and the first conductive pattern 16. Thereafter, a photoresist pattern 28 having an opening 27 is formed on the second conductive layer 26. The photoresist pattern 28 is formed such that the opening 27 defines a top of the active region 11 as well as the first conductive pattern 16. A portion of the second conductive layer 26 is exposed by the opening 27.
Referring to FIG. 1c, by using the photoresist pattern 28 as an etching mask, various layers, e.g., the capping layer, the first conductive layer and the ONO layer, below the second conductive layer 26 as well as the second conductive layer 26 are etched at the same time. Therefore, a pair of split-gates are formed on the active region 11 of the substrate, wherein the split-gates include the ONO layer 14, the first electrode 16a and the capping layer patterns 18a and 20a from a bottom and the second electrode 26a extending to the sidewall of the first electrode from a top of the capping layer patterns. The pair of the split-gates form the word line in a direction vertical to the bit line.
Meanwhile, FIG. 2a shows a top view of a substrate formed thereon a pair of first electrodes 16a and a pair of second electrodes 26a, and FIG. 2b shows a vertical cross-sectional view of a split gate at an end portion of a word line.
Referring to FIG. 2a and FIG. 2b, the pair of first electrodes 16a and the pair of second electrode 26a formed through the etching process of FIG. 1c are arranged to face each other; and, by exposing a common source(or a drain) region A between the pair of first electrodes 16a and the pair of second electrode 26a, a common line is formed in order to connect each of the memory cells to the exposed common source region A in parallel. In the conventional method, as shown in FIG. 1a, in order to form the first conductive pattern 16, the poly silicon layer and the capping layers are sequentially formed on a previously formed charge storage layer 14 and the first conductive pattern 16 parallel to the word line is formed by patterning the poly silicon layer and the capping layer simultaneously. And, the sidewall oxide layer 22 is formed by oxidizing the sidewall of the formed first conductive pattern 16. At this time, the formed sidewall oxide layer 22a has a shape that a central portion thereof is further thicker than both top and bottom end portions thereof by a smiling phenomenon.
Therefore, as shown in FIG. 1c, in case when the first conductive layer and the second conductive layer are patterned at the same time, byproducts such as polymers formed during the etching process remain at a region B of a lower portion, i.e., a portion of the second conductive layer around one end portion of the word line, of the smiling type sidewall oxidation layer B, thereby generating a conductive stringer R. Through an image of the scanning electron microscope(SEM) shown in FIG. 3, it is possible to identify that the conductive stringer remains at one end portion of the word line. As shown in FIG. 2a, the conductive stringer F formed like this causes a short between the pair of second electrodes 26a facing each other, thereby deteriorating a performance of the device.